1. Technical Field
The disclosure relates to a magnetic shift register memory and the operation thereof.
2. Technical Art
Magnetoresistive Random Access Memory (MRAM) has advantages of non-volatility, high density, fast read/write speed, radiation resistance, and so on. Such features make the MRAM a potential candidate to replace the conventional semiconductor memory and to provide embedded memory applications. A conventional magnetic writing MRAM device uses metal lines for current conduction, sensing the magnetic field, and switching the free layer of the MRAM. With to size reductions come a significant increase in demagnetization effects and the write current requirement. Therefore, this type of MRAMs suffers from various difficulties in scalibility. Spin-torque transfer switching (STT), also known as Spin-RAM, is a next generational writing magnetic memory technique proposed in the recent years. Since the write current directly flows to the memory element, with the size of memory decreasing, the write current requirement also accordingly decreases. Hence, this type of memory features ease of scaling. However, the STT technique has questionable device thermal stability, an overly large write current requirement, as well as reliability concerns. These factors hamper the mass production potential of this type of memory.
Other conventional techniques also use current pulses to induce current-driven domain wall motion, and these techniques were proposed and developed between 1998 and 2004. U.S. Pat. No. 6,834,005 B1 has proposed the magnetic shift register memory, a device structure capable of drastic increase in chip or hard drive data storage volume. This type of memory has the possibility of replacing the DRAM, the SRAM, the FLASH memory, and may even make “disk drive on a chip” to be possible. This type of memory has magnetic disks similar to ones in hard drives, but folded into a 3D stacking structure for storage. Current-driven domain wall motion is used to record data sequentially into the disks, and operational speed exceeds the FLASH chip and the hard drive.
FIGS. 1A-1C represent schematic diagrams illustrating the operation of a conventional magnetic shift register memory. A memory device 100 includes a storage region 35, a reservoir region 40, a writing device 15, and a reading device 20. The memory device 100 can be a shift register memory comprising of magnetic metallic materials such as the NiFe, CoFe, or similar ferromagnetic materials that can provide data storage and a track 11 for motion. A plurality of small magnetic domains 25 and 30 can be magnetized on track 11. The magnetization directions of the magnetic domains can represent the logic 0 or 1 value of the storage data. Track 11 of the magnetic shift register memory is serially coupled with a neighboring track. A set of writing device 15 and reading device 20 form a set of memory region. Each memory region includes the storage region 35 and the reservoir region 40. While data storing is at the quiescent state, or a stable state not having current-driven domain wall motion, a plurality of memory units such as the magnetic domain 25 representing data 0 and the magnetic domain 30 representing data 1 are sequentially stored in the storage region 35. The reservoir region 40 does not have data stored at this time. The reading device 20 of the magnetic shift register memory is coupled to the track 11 by a magnetic tunneling junction (MTJ). Data bits are sequentially read by passing through current pulses 45, where each of the magnetic domains 25 and 30 has domain wall motion (DWM) towards the direction of electron flow.
FIG. 1B illustrates a pause status, in which a nearest data bit of the reading device 20 can be read, the previously read data bit is moved into the reservoir region 40 until all the data bit stored in the storage region 35 have been read, then all the data bits are moved into the reservoir region 40, and thereafter using current pulses 45 of a reverse direction to move all the data bits back to the storage region 35. When the magnetic shift register memory is writing data, or passing through current pulses 45 to move the magnetic domain for data writing to the writing device 15. At this time, another writing line employing domain wall motion moves a stray field having a predetermined direction into the writing region, thereby causing the magnetic domain to spin to the desired direction for data writing, and thereafter the data in the magnetic domain is sequentially moved back to their original position by current pulses 45 having a reverse direction. According to common knowledge for a memory, the reading device 20 uses a select transistor (e.g. a MOS transistor) coupled to a sense amplifier. The select transistor occupies the surface area of the Si substrate, and the size of data magnetic domains 25 and 30 is usually much smaller than the select transistor. Therefore, the effective size of the magnetic shift register memory is determined by the occupied area of the select transistor, as well as a set of transistors for controlling the data bits (magnetic domains 25 and 30) stored in the storage region 35. Since the magnetic shift register memory includes a plurality of bits, the effective bit size can be decreased.
FIG. 2 represents a schematic diagram illustrating a plurality of mechanisms depicted in FIGS. 1A-1C. Referring to FIG. 2 and simplifying the mechanism of FIG. 1, the magnetic shift register memory 100 is expanded on a linear track, in which the magnetic shift register memory 100 includes the storage region 35 and the reservoir region 40, each having a plurality of magnetic domains 25 and 30. As shown in FIG. 2, the storage region 35 of the magnetic shift register memory 100 records 4 bits of data that, can be moved into the reservoir region 40. FIG. 3 represents a schematic diagram illustrating a read mechanism. Referring to FIG. 3, an example of the reading mechanism can be applying a current pulse 106 to the magnetic shift register memory 100. The magnetic domains 102 and 104 are moved, and one of the magnetic domains 102 and 104 reads the data bits of the circuit 108 by reading the position thereof. On the other hand, data can be written into the magnetic domain by using a write circuit for writing in the data.
However, the conventional magnetic shift register memory design is still not optimal. The techniques for the magnetic shift register memory are in their early developmental phase, with manufacturers earnestly devoting research and development efforts.
In the above-described conventional designs, the magnetization direction of the magnetic domain is parallel to the magnetic track, thereby needing a larger width and thus increasing the size of the magnetic domains of the memory cells. There are conventional techniques proposing designs having the magnetization direction on the magnetic domain perpendicular to the magnetic track, thereby decreasing the size of the memory cell. However, such a perpendicular memory cell cannot move effectively on an U-shaped magnetic track. Therefore, the U-shaped magnetic track design is in need of improvements.